Chip

ABSTRACT

A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefits of U.S. provisional application Ser. No. 62/947,190, filed on Dec. 12, 2019, and Taiwan application serial no. 109116518, filed on May 19, 2020. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to a chip, and particularly to a chip having a flexible substrate.

Description of Related Art

In the prior art, in order to avoid cracking of a chip applied to a flexible substrate during repeated bending, the chip may not be provided with a multilayer metal wiring structure. In this case, fewer layers of metal wirings cause the transistor density in the chip to decrease and the manufacturing cost of the chip to increase.

SUMMARY OF THE INVENTION

The invention provides a chip applied to a flexible substrate. The chip may be provided with a multilayer metal wiring structure, and at the same time avoid the risk of cracking due to the multilayer metal wiring structure.

A chip of the invention includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.

Based on the above, the multilayer metal wiring structure is provided in the chip in a grid shape, so that the chip may effectively reduce the risk of cracking, thereby further increasing the transistor density in the chip and reducing the manufacturing cost of the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A is a cross-sectional view of a chip of an embodiment of the invention.

FIG. 1B is a cross-sectional view of a chip of another embodiment of the invention.

FIG. 2A to FIG. 2D are top views of power rail layers of embodiments of the invention viewed downward from the vertical direction.

FIG. 3A to FIG. 3D are diagrams of the arrangement of power rail layers of an embodiment of the invention.

FIG. 4A is a diagram of the arrangement of power rail layers of an embodiment of the invention.

FIG. 4B is a diagram of the arrangement of power rail layers of an embodiment of the invention.

FIG. 4C is a diagram of the arrangement of power rail layers of an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1A is a cross-sectional view of a chip 1 a of an embodiment of the invention. The chip 1 a includes a flexible substrate 10, a plurality of thin-film transistors (TFTs) 11, a redistribution layer 12, and power rail layers 13 and 14. In the chip 1 a shown in FIG. 1A, the number and arrangement relationship of the thin-film transistors 11 may be adjusted according to different design requirements, and the invention is not limited thereto. The thin-film transistors 11 are disposed on the flexible substrate 10. The redistribution layer 12 is disposed on the plurality of thin-film transistors 11. The power rail layer 13 is disposed on the redistribution layer 12. The power rail layer 14 is disposed on the power rail layer 13. Overall, by disposing the power rail layers 13 and 14 on the redistribution layer 12, the chip 1 a may effectively increase the transistor density in the chip 1 a and reduce the area required by the chip 1 a, so the chip 1 a may effectively reduce manufacturing cost.

In detail, the flexible substrate 10 has the characteristic of being bendable, and the flexible substrate 10 may be made of a material such as polyimide (PI). The bendable radius of curvature of the flexible substrate 10 is less than a predetermined radius of curvature. In an embodiment, the bendable radius of curvature of the flexible substrate 10 may be less than 25 millimeters (mm). Since the cost of the flexible substrate 10 in the chip 1 a accounts for most of the manufacturing cost of the chip 1 a, reducing the area of the flexible substrate 10 in the chip 1 a may effectively improve the manufacturing cost of the chip 1 a.

The plurality of thin-film transistors 11 are disposed on the flexible substrate. The thin-film transistors 11 may implement arithmetic or other operational functions in the chip 1 a. The redistribution layer 12 is disposed above the thin-film transistors 11, a through hole 12 v may be disposed between the redistribution layer 12 and the thin-film transistors 11, and the through hole 12 v may be a conductive structure. Therefore, the through hole 12 v may make the redistribution layer 12 electrically connected to the thin-film transistors 11. The redistribution layer 12 is patterned to be provided with a wiring structure, so according to the connection relationship provided by the redistribution layer 12 and the through hole 12 v, the thin-film transistors 11 may perform a pre-programmed computing operation. In an embodiment, the redistribution layer 12 may be made of gold, silver, copper, nickel, indium tin oxide (ITO), or other suitable materials and combinations thereof.

The power rail layer 13 is disposed above the redistribution layer 12. The power rail layer 13 may be connected to an external pad or a power circuit of the chip la to obtain a first voltage (for example, ground voltage). A through hole 13 v may be disposed between the power rail layer 13 and the thin-film transistors 11. The through hole 13 v may be a conductive structure. Therefore, the through hole 13 v may provide an electrical connection between the power rail layer 13 and the thin-film transistors 11. The power rail layer 13 is patterned to be provided with a wiring structure. Therefore, via the power rail layer 13 and the through hole 13 v, the thin-film transistors 11 may receive a first voltage (for example, ground voltage) required for operation. In an embodiment, the power rail layer 13 may be made of gold, silver, copper, nickel, indium tin oxide (ITO), or other suitable materials and combinations thereof.

The power rail layer 14 is disposed above the power rail layer 13. The power rail layer 14 may be connected to an external pad or a power circuit of the chip 1 a to obtain a second voltage (for example, operating voltage). A through hole 14 v may be disposed between the power rail layer 14 and the thin-film transistors 11. The through hole 14 v may be a conductive structure. Therefore, the through hole 14 v may provide an electrical connection between the power rail layer 14 and the thin-film transistors 11. The power rail layer 14 is patterned on top to be provided with a patterned wiring structure. Therefore, via the power rail layer 14 and the through hole 14 v, the thin-film transistors 11 may receive a second voltage (for example, operating voltage) required for operation. In an embodiment, the power rail layer 14 may be made of gold, silver, copper, nickel, indium tin oxide (ITO), or other suitable materials and combinations thereof.

Furthermore, since the chip 1 a is flexible and has a multilayer structure, in order to improve the flexibility of the chip 1 a, the power rail layer 14 in the chip 1 a is disposed in a grid shape. In this way, the chip 1 a has better consistency in both process uniformity and surface flatness. In other words, the grid-shaped power rail layer 14 may provide the chip 1 a with better flexibility to avoid cracking in the chip 1 a.

Although in the cross-sectional view shown in FIG. 1A, the through holes 12 v, 13 v, and 14 v are overlapped with each other, those skilled in the art know that the through holes 12 v, 13 v, and 14 v may be structures separated from each other when viewed from top to bottom in the vertical direction of the chip 1 a. Therefore, the redistribution layer 12 and the power rail layers 13 and 14 may be electrically connected to the thin-film transistors 11 via the mutually independent paths of the through holes 12 v, 13 v, and 14 v.

Therefore, by disposing the additional power rail layers 13 and 14 on the redistribution layer 11, and by disposing the power rail layers 13 and 14 in a vertical layered structure, the issue of excessive area of the redistribution layer 12 caused by disposing the power rails in the redistribution layer 12 may be effectively avoided. In other words, the additional power rail layers 13 and 14 of the chip 1 a may effectively reduce the separation distance of the thin-film transistors 11 in the chip 1 a, increase the density of the thin-film transistors 11 in the chip 1 a, and at the same time reduce the area of the flexible substrate 11 required for the chip 1 a. Therefore, the manufacturing cost of the chip 1 a may be effectively reduced.

FIG. 1B is a cross-sectional view of a chip 1 b of another embodiment of the invention. The chip 1 b shown in FIG. 1B is similar to the chip 1 a shown in FIG. 1A, so the same elements adopt the same reference numerals, and the description of the same elements is provided in related paragraphs above and is not repeated herein. The difference between the chip 1 b and the chip 1 a is that the chip 1 b is also provided with an antenna 15 above the power rail layer 14.

In detail, in some embodiments, the chip 1 b must be provided with an antenna structure to meet specific system requirements. In the present embodiment, the antenna 15 is disposed above the power rail layer 14. A through hole 15 v may be disposed between the antenna 15 and the thin-film transistors 11, and the through hole 15 v may be a conductive structure. Therefore, the through hole 15 v may provide an electrical connection between the antenna 15 and the thin-film transistors 11. The antenna 15 is patterned on top to be provided with a patterned antenna structure. Therefore, the antenna structure on the antenna 15 may receive and send a signal for the thin-film transistors 11. In an embodiment, the antenna 15 may be made of gold, silver, copper, nickel, indium tin oxide (ITO), or other suitable materials and combinations thereof.

Furthermore, the antenna 15 may be receive or send a wireless signal for the chip 1 b, and therefore the frequency of the signal transmitted and received on the antenna 15 is higher than the signal operated by most of the thin-film transistors 11. In the chip 1 b, the distance between the antenna 15 and the thin-film transistors 11 may be effectively increased due to the redistribution layer 12 and the power rail layers 13 and 14. In an embodiment, the distance between the antenna 15 and the thin-film transistors 11 is greater than 13 micrometers, so the interference of the high-frequency signal of the antenna 15 on the operation signal of the thin-film transistors 11 may be effectively reduced. Moreover, since a first voltage (for example, ground voltage) and a second voltage (for example, operating voltage) of direct current are provided on the power rail layers 13 and 14 respectively, the power rail layers 13 and 14 may provide good signal shielding between the antenna 15 and the thin-film transistors 11, so the chip 1 b may effectively resist the high-frequency noise of the antenna 15 coupled to the thin-film transistors 11.

In short, the structures of the thin-film transistors 11, the redistribution layer 12, the power rail layers 13 and 14, and the antenna 15 in the chip 1 b may effectively improve the signal integrity of the chip 1 b. Therefore, the chip 1 b may not only effectively reduce the manufacturing cost, but also significantly improve the signal integrity.

FIG. 2A to FIG. 2D are top views of power rail layers 14 a to 14 d of a plurality of embodiments of the invention viewed downward from the vertical direction. In detail, the power rail layers 14 a to 14 d may be applied to the chips 1 a and 1 b shown in

FIGS 1A and 1B. The power rail layers 14 a to 14 d may have a greater area. In response to the design requirements of different chips, the power rail layers 14 a to 14 d may have different grid shapes.

As shown in FIG. 2A, the grid shape of the power rail layer 14 a has a rectangular outer contour, the inside of the outer contour is provided with a straight and staggered power rail, and a plurality of rectangular grid holes are formed on the inside to form the grid-shaped power rail 14 a.

As shown in FIG. 2B, the power rail layer 14 b may be provided with a plurality of power rails parallel to a first direction (for example, lateral direction) at a first interval in the power rails with a rectangular contour, and one or a plurality of rectangular power rails may be disposed in a second direction (for example, vertical direction) in the power rails with a rectangular contour, which penetrate the overall rectangular contour to form the grid-shaped power rail 14 b.

As shown in FIG. 2C, the power rail layer 14 c may have a plurality of rectangular power rails, and the power rails with a rectangular contour are staggered with each other to form the grid-shaped power rail 14 c.

As shown in FIG. 2D, the power rail layer 14 d may be regularly provided with a plurality of power rails with a greater width at a first interval in a first direction (for example, lateral direction), and be regularly provided with a rectangular power rail with a smaller width at a second interval in a second direction (for example, vertical direction), thereby forming the grid-shaped power rail 14 d.

Therefore, the power rail layers 14 a to 14 d are disposed in the chips 1 a/1 b in a grid shape to improve the process uniformity and surface flatness of the chips 1 a/1 b, so that the chips 1 a/1 b have better flexibility. Moreover, via the grid-shaped power rail layers 14 a to 14 d, the arrangement density of power rails and the capacitance of the power rails may be increased, thereby effectively reducing the disturbance of the second voltage (for example, operating voltage) in the chips 1 a/1 b and improving the signal quality of the chips 1 a/1 b. In short, by disposing power rails in a grid shape on the power rail layers 14 a to 14 d, while increasing the laying density of the power rail layers 14 a to 14 d and improving the signal quality of the chips 1 a/1 b, the chips 1 a/1 b may adapt to different design requirements to increase the design flexibility of the chips 1 a/1 b.

FIG. 3A is a diagram of the arrangement of a power rail layer 14 e of an embodiment of the invention. A portion of the components in the chips 1 a/1 b is omitted in FIG. 3A to facilitate understanding of the arrangement of the power rail layer 14 e. In the present embodiment, the thin-film transistors 11 may form circuit blocks B1 to B4. The power rail layer 14 e above the circuit block B1 may be a closed plane. In addition, the power rail layer 14 e above the circuit block B2 may have an opening to expose the circuit block B2. The power rail layer 14 e above the circuit blocks B3 and B4 may have a grid shape to partially cover the circuit blocks B3 and B4. In other words, when viewed downward in the vertical direction of the power rail layer 14 e, the circuit block B1 may be completely covered by the power rail layer 14 e, the circuit block B2 may be exposed, and the circuit blocks B3 and B4 may be partially covered by the power rail layer 14 e. Therefore, due to different design considerations, for example, the structure of the circuit block B1 needs to be covered to better protect the circuit structure, or the structure of the circuit block B2 needs lower noise interference and is not to be covered by the power rail layer 14 e. In the above situation, the power rail layer 14 e may be flexibly disposed in a diverse manner according to the different needs of the power blocks B1 to B4.

FIGS. 3B and 3C are diagrams of the arrangement of power rail layers 14 f and 14 g of an embodiment of the invention. A portion of the components in the chips 1 a/1 b is omitted in FIGS. 3B and 3C to facilitate understanding of the arrangement of the power rail layers 14 f and 14 g. In FIGS. 3B and 3C, the thin-film transistors 11 may be divided into a thin-film transistor 11 a and a thin-film transistor 11 b, and the thin-film transistor 11 a and the thin-film transistor 11 b have different first conductivity type and second conductivity type, respectively. For example, the thin-film transistor 11 a may be an N-type thin-film transistor, and has a low-voltage conductivity type. The thin-film transistor 11 b may be a P-type thin-film transistor, and has a high-voltage conductivity type. Therefore, the conductivity types of the thin-film transistors 11 a and 11 b are complementary. The conductivity types of the thin-film transistors 11 a and 11 b are different. The structure of the power rail layer 14 f shown in FIG. 3B is similar to the power rail layer 14 b shown in FIG. 2B. The structure of the power rail layer 14 g shown in FIG. 3C is similar to the power rail layer 14 c shown in FIG. 2C. In the present embodiment, the power rail layers 14 f and 14 g may be partially covered on the thin-film transistors 11 a and 11 b. More precisely, the power rail layers 14 f and 14 g may be covered above the drain regions and the source regions of the thin-film transistors 11 a and 11 b and expose the gate regions of the thin-film transistors 11 a and 11 b. In this way, while protecting the circuit structure, the power rail layers 14 f and 14 g may also prevent excessive parasitic capacitance between the gates of the thin-film transistors 11 a and 11 b and the power rail layers 14 f and 14 g from affecting the signal quality of the thin-film transistors 11 a and 11 b.

FIG. 3D is a diagram of the arrangement of a power rail layer 14 h of an embodiment of the invention. The structure of the power rail layer 14 h shown in FIG. 3D is similar to the power rail layer 14 d shown in FIG. 2D. In the present embodiment, the power rail layer 14 h may completely cover the thin-film transistors 11 a and 11 b, so the power rail layer 14 h may achieve a better protection effect for the circuit structure in the chips 1 a/1 b.

Although FIGS. 2A to 2D and 3A to 3D only describe the power rail layers 14 a to 14 h, the invention is not limited thereto. In other words, the power rail layer 13 in the chips 1 a/1 b may also be disposed in a grid shape to achieve a similar effect to the power rail layers 14 a to 14 h.

FIG. 4A is a diagram of the arrangement of power rail layers 13 i and 14 i of an embodiment of the invention. The power rail layer 13 i may transmit a first voltage (for example, ground voltage) to the chips 1 a/1 b, and the power rail layer 14 i may transmit a second voltage (for example, operating voltage) to the chips 1 a/1 b. In the embodiment shown in FIG. 4A, when the power rail layers 13 i and 14 i are viewed downward in a vertical direction, the power rail layers 13 i and 14 i may be arranged alternately. The power rail layer 13 i is covered above the thin-film transistor 11 a (not shown in FIG. 4A) having a first conductivity type. The power rail layer 13 i may transmit the first voltage to the thin-film transistor 11 a having the first conductivity type via the through hole 13 v. The power rail layer 14 i is covered above the thin-film transistor 11 b (not shown in FIG. 4A) having a second conductivity type. The power rail layer 14 i may transmit the second voltage to the thin-film transistor 11 b having the second conductivity type via the through hole 14 v.

FIG. 4B is a diagram of the arrangement of power rail layers 13 j and 14 j of an embodiment of the invention. In the embodiment shown in FIG. 4B, the power rail layer 13 j is covered above the thin-film transistor 11 a having the first conductivity type. The power rail layer 13 j may transmit a first voltage to the thin-film transistor 11 a (not shown in FIG. 4B) having a first conductivity type via the through hole 13 v. The power rail layer 14 j is covered above all the thin-film transistors 11 a and 11 b (not shown in FIG. 4B). The power rail layer 14 j may transmit a second voltage to the thin-film transistor 11 b having a second conductivity type via the through hole 14 j.

FIG. 4C is a diagram of the arrangement of power rail layers 13 k and 14 k of an embodiment of the invention. The power rail layers 13 k and 14 k shown in FIG. 4C are respectively similar to the power rail layers 13 j and 14 j shown in FIG. 4B, except that in FIG. 4C, the power rail layer 14 k may additionally be provided with a power rail layer 13′ on a path on which the second voltage is transmitted to the thin-film transistor 11 b via the through hole 14 v. The power rail layer 13′ may be disposed on the same structure layer as the power rail layer 13 k, but the power rail layer 13′ is not electrically connected to the power rail layer 13 k. Therefore, in the embodiment shown in FIG. 4C, the power rail layer 13 k is covered above the thin-film transistor 11 a having a first conductivity type. The power rail layer 13 k may transmit a first voltage to the thin-film transistor 11 a (not shown in FIG. 4C) having the first conductivity type via the through hole 13 v. The power rail layer 13′ is covered above the thin-film transistor 11 b having a second conductivity type. The power rail layer 14 k is covered above all the thin-film transistors 11 a and 11 b (not shown in FIG. 4B). The power rail layer 14 j may transmit a second voltage to the thin-film transistor 11 b having the second conductivity type via the through hole 14 j and the power rail layer 13′.

Based on the above, the multilayer metal wiring structure is provided in the chip of the invention in a grid shape, so that the chip may effectively reduce the risk of cracking, thereby further increasing the transistor density in the chip and reducing the manufacturing cost of the chip. 

What is claimed is:
 1. A chip, comprising: a flexible substrate; a plurality of thin-film transistors disposed on the flexible substrate; a redistribution layer disposed above the thin-film transistors; a first power rail layer disposed above the redistribution layer to provide a first voltage to the thin-film transistors; and a second power rail layer disposed above the first power rail layer to provide a second voltage to the thin-film transistors, wherein the second power rail layer is disposed in a grid shape.
 2. The chip of claim 1, further comprising an antenna disposed above the second power rail layer, wherein the antenna is coupled to the thin-film transistors.
 3. The chip of claim 1, wherein a distance between the antenna and the thin-film transistors is greater than 13 micrometers.
 4. The chip of claim 1, wherein a bendable radius of curvature of the flexible substrate is less than a predetermined radius of curvature.
 5. The chip of claim 1, wherein the flexible substrate comprises polyimide (PI).
 6. The chip of claim 1, wherein in a vertical projection of the chip, the second power rail layer at least partially covers the thin-film transistors.
 7. The chip of claim 6, wherein the second power rail layer covers a drain region and a source region of the thin-film transistors.
 8. The chip of claim 6, wherein the thin-film transistors form a plurality of circuit blocks, and the second power rail layer covers a first circuit block in the circuit blocks.
 9. The chip of claim 6, wherein the thin-film transistors may be divided into a plurality of first thin-film transistors and a plurality of second thin-film transistors, the first thin-film transistors have a first conductivity type, the second thin-film transistors have a second conductivity type, and the first conductivity type is different from the second conductivity type.
 10. The chip of claim 9, wherein the first power rail layer covers the first thin-film transistors, and the second power rail layer covers the second thin-film transistors.
 11. The chip of claim 10, wherein the first power rail layer and the second power rail layer are staggered.
 12. The chip of claim 9, wherein the first power rail layer covers the first thin-film transistors, and the second power rail layer covers all the thin-film transistors.
 13. The chip of claim 6, wherein the first power rail layer covers all the thin-film transistors, and the second power rail layer covers all the thin-film transistors. 